A local area computer network comprises a relatively small data communication system, usually within the confines of several thousand meters, for example, for the interconnection of a plurality of terminal or user devices or hosts, e.g., workstations. The protocol scheme, operational bandwidth and specifications of the network are such that high speed communication among such devices is possible. An overall methodology is to provide hosts, each capable of performing a plurality of computer aided functions independent of any other host coupled to the network, with means to access the network toward the overall goal of intercooperative data communication and improved efficiency in the use of time in conducting business.
A local area computer network generally takes the form of one of three basic topologies, a star, ring or bus. Each such network comprises several basic components. These components include a transmission medium, two or more stations or hosts and an interface to couple the hosts to the medium. The host makes direct communicative use of the communication channel and is generally a smart terminal. Specialized I/O devices, such as magnetic tape and disk drives, may include sufficient computing resources to function as "hosts" on a network. The transmission medium may be radio, coaxial cable, twisted wire pair or optical fiber. Repeaters may be used along the medium to extend the length of the transmission system beyond the physical constraints imposed by the medium.
The interface includes two basic components, a communication manager, e.g., a controller, and, in most cases, a transceiver. The controller for a host is the set of functions and algorithmic implementation necessary to manage host access to the medium. The basic functions include signal and data handling and transmission management, e.g., signalling conventions, encoding and decoding, serial-to-parallel conversion and vice versa, address recognition, error detection, buffering and packetization. These functions can be grouped into two logically independent sections of the controller: the transmitter section and the receiver section.
The transceiver contains the electronics to transmit and receive signals to and from the communication medium. A transceiver recognizes the presence of a signal when another host transmits and recognizes a collision that takes place when two or more hosts transmit simultaneously.
An example of a bus oriented local area network is called "Ethernet" and is basically disclosed in U.S. Pat. Nos. 4,063,220 and 4,282,512, assigned to the assignee herein, and is also discussed in the publication "The Ethernet Local Network: Three Reports" published by Xerox Corporation, February, 1980 and in the Ethernet Specifications published Sept. 30, 1980 by Digital Equipment Corporation, Intel Corporation and Xerox Corporation. Ethernet transmission of data signals is by means of packetized data bursts. Each packet contains the identification of the source and destination of that packet, along with a data field generally containing multiple digital data items. Packets are transmitted, for example, along a 50.OMEGA. coaxial cable at 10 Mbits/sec.
Access to the cable is by contention, using a carrier-sense multiple-access with collision-detection (CSMA/CD) technique. A characteristic of this technique, as in all packet transmission networks, is that access time to the network depends on traffic load. In a CSMA/CD system, stations contend for use of the common broadcast communications channel until one of them acquires access and then uses the cable to transmit a packet. Access is obtained by listening for activity on the cable, termed as "carrier sense". If carrier sense is true, transmission is deferred until the channel is quiet, i.e., no other carriers are present. When the channel is quiet, the workstation desiring access can proceed with transmission.
During transmission, the station listens for a collision due to any other carrier that may be on the channel. Since other stations will defer once they see a carrier, the first round-trip propagation time is the only time that such collisions can occur in the network. If no other carrier is sensed or detected within one-round trip time, the station is said to have acquired the channel. If another carrier is sensed in this time frame, the transmission of the packet is aborted and a jam signal is transmitted to ensure that the collision is also detected by all other stations connected to the channel. After jamming, each station waits a random length of time via a back off algorithm and tries again for access to the communication channel. Further details concerning the operation and specifications of this type of system are found in the previously mentioned publications.
With the development of integrated circuitry and, in particular, MOS/VLSI technology, e.g., nMOS, there is a standing desire to provide one or more of the basic components of a local area computer network in the form of an integrated semiconductor chip. This need is important for the interface or controller because if the size, and correspondingly the cost, of the controller can be reduced, availability of its use in many different types of smart terminal devices providing therein each with their own communication capability with other smart terminals. For example, it would be desirable to provide network communication and access by standard "smart" word processors. However, the cost of the presently available controllers is prohibitive for such applications. If a controller is fabricated as a MOS/VLSI semiconductor chip, a hugh reduction in cost can be realized permitting feasible commercial use of such a chip in any low cost standard processor for which communication of data over a network is desired.
Prior art data and clock recovery systems employ discrete circuit components that change in value over time continually requiring adjustment. This can be quite costly in technical maintenance when equipment is in the field. An example of such a recovery system is the phase or data/clock recovery circuit 332 disclosed in FIG. 6 of U.S. Pat. No. 4,063,220. Beside comprising a plurality of independent discrete devices, the propagation delay rate provided by the transition detector 700, which is a time delay circuit, is not continually the same due to changes, for example, in the operation of the one shot multivibrator 703. As a result, upon recovery of data from the data packet on line "i" to the data recovery device 704, the point of sampling may not be continually correct.
U.S. Pat. No. 4,287,596 also discloses a data and clock recovery system for the data processing system shown in FIG. 1. The system, like that of U.S. Pat. No. 4,063,220, includes a time delay circuit for the signal which provides the timing for subsequent data and clock recovery. Again, dependence is had on discrete components and circuit devices that cannot be continually relied upon to provide a continually precise delayed signal.
A more recent version of a data and clock recovery has been a phase lock loop (PLL) circuit employed in local area network workstations. This circuit suffers from the same problem as the multivibrator version in that each of the versions lack any continually guaranteed degree of signal delay accuracy due to the variable properties of discrete electrical components, in particular, capacitors in the circuits providing an RC time constant which must be periodically adjusted.
What is desired is some means of eliminating the use of these discrete components by MOS/VLSI implementation and also providing some guarantee of self-calibration to ensure continually accurate signal delay.
While MOS/VLSI implemention of the circuitry for a controller is very desirable, problems are encountered in employing MOS technology because minute changes in parameters that occur during fabrication. Die from one wafer to the next during successive wafer processing may readily have different transistor electrical properties. Uniformity in said properties are very important and crucial in electrical circuitry where clock synchronization and timing, for example, must be fairly precise in order to meet protocol specifications of the network and accurate decoding of received data.
An example of the precise timing necessary in controller circuitry is the encoding and decoding employed in the Ethernet local area computer network. The channel encoding employed is Manchester phase encoding with a data rate of 10 Mbits/sec with each bit cell 100 ns long. During the first half of each bit cell time (e.g., 0-50 ns) the serial data signal transmitted is the logical complement of the bit value being encoded during that cell. During the second half of the bit cell time (e.g. 50-100 ns), the uncomplemented value of the bit being encoded is transmitted. Thus, there is always a data signal transition either positive-going or negative-going in the center of each bit cell. During decoding, it is necessary to separate the incoming phase encoded bit stream into a data stream and a clock signal. If timing on the chip is not accurate so that the moment of signal sampling for data recovery is at the time of the data signal transition for each data cell, the data will be lost or not accurately decoded.
What is needed is some manner of implementation of the controller in MOS/VLSI technology while easily replicating integrated circuit characteristics in a uniform behavior in timing and the decoding of received data signals or packets in a data communication controller.